VHDL 360, Modeling Finite State Machines (FSMs)

• What is a FSM?
• State Machine
• Moore FSM
• Moore Implementation
• Mealy FSM
• Mealy Implementation
• FSM in VHDL
• Next State Logic
• Current State Logic
• Assigning Moore Outputs
• Assigning Mealy Outputs
• Moore vs. Mealy
• FSM Tips
• Example
• Exercise 1: Simple Control Unit
• State Machine Encoding
• Exercise 2: Traffic Light Controller

Modeling FSMs

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