Android Booting Scenarios

Recently, I was trying to dig more into the Android kernel all over the net.

My concern was to understand the booting scenarios of this kernel.

I tried to make the task either by collecting them into the slides below.

These slides are a part of course I am currently preparing about the Android Internals.

Waiting for your comments.

Android Booting Scenarios from amraldo

VHDL 360, Simulation using ISIM

• Creating Project
• Interactive Simulation

Simulation Using Isim

View more PowerPoint from amraldo

SECC: Embedded SW Training July 2011

 SECC is organizing the following courses  in the:

Embedded Software Training Track

From 3 to 21 July 2011

Schedule , Fees &  Instructors:

http://www.secc.org.eg/Schedule/Embedded_Software/Embedded_Schedule_2011.pdf

 Registration:

Please fill in & submit your registration form at:

       http://www.secc.org.eg/Embedded_Registration.asp

      before end of  Sunday June 19, 2011

Outline  :

Kindly find attached the courses outline

About Training :

§  Training day starts from 9:00 AM to 4:00 PM

§  The courses will be held at the Smart Village – Building B121 - Km 28 Cairo-Alex  desert Road.

About fees:

     After you receive SECC confirmation email:

• The fees will be paid at:  Smart Village -  SECC premises -  B121 – ITIDA Building

• Attention  Mr. Ahmed Anany – room 1017,   tel.: 35345250,  mobile:0101709913

Cancellation Policy

·               Only 5 working days before the beginning of the course, the applicant can be totally refunded. ·               Other than that there is no refund

For any further information please don't hesitate to contact us

Ø  Mr. Mohammed Bhady   : 35345226

Ø  Mr. Mahmoud Mansour : 35345122

VHDL 360, Structural Description

• How to Create Your Generic DU?
• Generic Clause
• Exercise 1: N Input OR Gate
• Exercise 2: N Input AND Gate
• Structural Description
• Structural Modeling
• Component Instantiation
• Exercise 3: Use T-FF to Create a 2-Bit Counter
• Testbench
• Stimulus Generation
• Monitors
• Generate Statement
• Exercise 4: Create N-Bit Shift Register
• VHDL Configurations

Building Hierarchy

View more presentations from Mohamed Samy.

VHDL 360, Modeling Finite State Machines (FSMs)

• What is a FSM?
• State Machine
• Moore FSM
• Moore Implementation
• Mealy FSM
• Mealy Implementation
• FSM in VHDL
• Next State Logic
• Current State Logic
• Assigning Moore Outputs
• Assigning Mealy Outputs
• Moore vs. Mealy
• FSM Tips
• Example
• Exercise 1: Simple Control Unit
• State Machine Encoding
• Exercise 2: Traffic Light Controller

Modeling FSMs

View more presentations from Mohamed Samy.

VHDL 360, Synthesis Examples

• Introduction
• Synthesize and Learn
• Combinational Logic
• Latch Inference
• Sequential Logic
• Flip-flop Interference

Synthesis Examples

View more presentations from Mohamed Samy.

VHDL 360, Data Types and Operators Continued

• Operators
• Operators Precedence
• Logical Operators
• Addition Operators
• Relational Operators
• Shift Operators
• Multiplication Operators
• Miscellaneous Operators
• Aggregate
• Attributes

Data types and Operators Continued

View more presentations from Mohamed Samy.

VHDL 360, Data Types and Operators

• Data Types
• Scalar Types
• Composite Types
• Exercise 1: Modeling a 16x16 ROM Memory
• Exercise 2: Modeling 1024x8 RAM Memory

Data types and Operators

View more presentations from Mohamed Samy.

VHDL 360, Write More Complex Models Continued

• While Loop
• For Loop
• Exercise 1: Serial In Parallel Out
• Wait Statement
• Conversion Functions
• Lab 1.a: Write the Code for a Fibonacci Sequence
• Lab 1.b: Write the Code for Knight Rider LEDs

Writing more complex models (continued)

View more presentations from Mohamed Samy.

VHDL 360, Write More Complex Models

• Statements
• Process Description
  
• Sequential Assignments
  
• Data Objects
  
• Objects Scope
  
• Data Objects Example
  
• Skills Check
• Case Statement
• Exercise 1: 2x4 by Decoder
• If Statement
• Exercise 2: D FF with Synchronous Reset
• Exercise 3: Simple Comparator

Writing more complex models

View more presentations from Mohamed Samy.

VHDL 360, Create Your First Model for a Simple Logic Circuit

• Entity
• Exercise 1: Write the Entity of a 1-bit Full Adder
  
• Architecture
• Internal Signals
• Expressions & Operators
• Exercise 2: Write the Architecture of a 1-bit Full Adder
  
• With-Select
• When-Else
• Exercise 3: Write the Entity and Architecture of 2x4 Decoder and 4x2 Encoder using With-Select and When-Else

Create your first model for a simple logic circuit

View more presentations from Mohamed Samy.

FreeRTOS Course - Semaphore/Mutex Management

• Binary Semaphore
• Counting Semaphore
• Mutex
• More about Semaphore/Mutex
• Semaphore/Mutex Management APIs
• Lab4: Semaphore Mutex Management
  

FreeRTOS Course - Semaphore/Mutex Management

View more presentations from amraldo.

Free RTOS Course - Queue Management

• Queues
• More About Queues
• Queue Management APIs
• Lab 3: Queue Management
  

FreeRTOS Course - Queue Management

View more presentations from amraldo.

VHDL 360, Introduction to VHDL

• What is VHDL?
• VHDL History
• Uses of VHDL
• Basic Design Flow
• VHDL Model
• Entity
• Architecture
  
• Concurrency
• Simple Example

Introduction to VHDL

View more presentations from Mohamed Samy.

VHDL 360, a Contribution from the SAMs

About VHDL

VHDL is a powerful language developed in the 1980's by the US department of defense, afterwards adopted by the IEEE to be a standard in 1987. Many enhancements & new features were added afterwards in the 1993, 2002 & 2008 standards...

VHDL is widely used around the word in the design & verification processes of High & Very High Scale integrated circuits design (HSI & VHSI)

About the Free Course, VHDL 360

VHDL 360 is a free course. During the course, SAMS will try to guide & teach students how to write efficient VHDL code to model digital circuits, the course outline will be as follows:

• Introduction to VHDL
• Writing 1st Model
• Writing more complex Models
• Building Hierarchy
• Modeling FSMs & Memories
• Code Reuse
• Verification

The course is based on VHDL IEEE 1076 - 1993 standard. It is vendor independent. Any text editor and tools you have license for can be used. Any consultation with regards to tools setup or support will not be provided and trainees should consult their own vendor for any of the issues or problems they face with this regards.

Feel free to post any comments, questions, and feedback through the blog. We promise to answer your questions as soon as possible Insha'Allah.

This VHDL course is for free use as long as the original copyright is reproduced. Feel free to spread and share. Knowledge is every body's right just like air and water.

Free FreeRTOS Course - Task Management

• Task C/Cs
• Task States and Transitions
• Task Priorities
• Implementing a Task
• Task's Hook
• Idle Task
• Idle Task Hook
• Task Management APIs
• Lab 2: Task Management
  

Free FreeRTOS Course-Task Management

View more presentations from amraldo.

Free FreeRTOS Course - Introduction to FreeRTOS

• At the Beginning
• FreeRTOS in Literature
• FreeRTOS History
• FreeRTOS V6.0.0
• FreeRTOS Features
• Related Products
• Licensing
• FreeRTOS Variants
• Free Support
• Lab 0: Getting Started
  

FreeRTOS Free Course

FreeRTOS the Real-Time Kernel

FreeRTOS is a small, yet powerful real-time operating system developed by Richard Barry and FreeRTOS Team and described in his book "Using the FreeRTOS Real-Time Kernel – a Practical Guide". The operating system is highly CPU independent and has been ported to numerous microprocessor platforms. The source code is available via this web site. It is distributed under the GPL with an optional exception. The exception permits users' proprietary code to remain closed source while maintaining the kernel itself as open source, thereby facilitating the use of FreeRTOS in proprietary applications.

FreeRTOS is designed to be small and simple. The kernel itself consists of only three or four C files. To make the code readable, easy to port, and maintainable, it is written mostly in C, but there are a few assembler functions included where needed (mostly in architecture specific scheduler routines). The download contains prepared configurations and demonstrations for every port and compiler, allowing rapid application design.

There are two forks of this OS; OpenRTOS and SafeRTOS. OpenRTOS, which has an identical code base to FreeRTOS but with different licensing. The OpenRTOS license removes all reference to the GPL and its implications. For example, one of the conditions of using FreeRTOS in a commercial product is that the user is made aware of the use of FreeRTOS and the source code must be provided upon request. OpenRTOS doesn't have this requirement. The other spin, SafeRTOS, is based on the FreeRTOS code base but has been updated, documented, tested and audited to enable its use in safety-critical products.

About the Free Course

The course scope is to teach students how to use FreeRTOS APIs. The course is based on V6.05. The course is organized in 8 modules. They are:

· Introduction to FreeRTOS

· Kernel Structure

· Task Management

· Queue Management

· Semaphore/Mutex Management

· Co-Routine Management

· Advanced Features

· FreeRTOS Porting

The labs for these modules are available based on the 80x86 industrial ports that use the open watcom compiler and ARM 7/Cortex that use the Keil compiler. Labs are only available commercially to our customers.

Feel free to post any comments, questions, ad feedback through the blog. I promise I will answer your post within 5 working days ISA.

This free course is for free use as long as the original copyright is reproduced. Feel free to spread, share, modify, or any other verb you can do with the material. Knowledge is every body's right just like air and water.

FreeRTOS GUI

After the course, I will publish a post on how to port an open source GUI for FreeRTOS. This post will help in demonstrating the power of FReeRTOS and how easily it can be extend with middleware. I have tested it only my PC. Work is currently on progress to test it on one of STM32 boards based on the ARM Cortex M3 processors.

My 2nd Visit to Anzma

About the Visit

My visit, this time, was more focused on uCOS-II. I challenged their students to finish a 4-hours lab based on the example, I developed earlier. The goal was to finish the lab in 4 hours and with maximum 8 questions. They were 5 students. Amazingly, the first finished his work after 2 hours only. It ran successfully from the first time. Other 3 students finished after 3 hours and half while the last finished just before the given time.

It was a great transition for the students and they gain confidence in themselves to code in a multi-task style. They proved the effectiveness and efficiency of Anzma's RTOS courses. In less than 16 hours, students were able to program a real application using uCOS-II.

Figure 1 shows me and the students after finishing the lab.

Figure 1: From the left to the right (Khaled, Ahmed, Me, Islam, Ahmed, and finally the champ Ibrahim)

My Visit to Anzma

About Anzma

Anzma & Cambridge Training College Britain are offering a complete integrated Embedded System Diploma to help fresh engineers to meld with the Embedded Systems industry, the new emerging career in Egypt.

We are offering a big step into the embedded systems’ world. To mould fresh computer science, computer engineers and, electronics engineers and to retrain working engineers into High Caliber Embedded System by enhancing their knowledge and skills in various design aspects of Embedded Systems. It provides an equal emphasis on both Software and Hardware platforms. This training is imparted to engineers aspiring to become Embedded Software Developers who want to tune up their skills in Embedded Software Development. This course will enhance the mutual understanding among different subjects through active interaction and exchange of ideas. This will enrich engineering education and practice through application of various aspects of real time system design to increase product value and to manage occupational constraints. The courses contents have been tuned up to prepare the engineers to fit with the real world industry organizations.

About the Visit

During the visit, I saw their RTOS track. The track is very comprehensive and up to the point. It consisted of 15 hours; 6 hours for Introduction to RTOS, and finally 6 hours for Introducing uCOS-II.

It was amazing to see trainees, and after 15 hours only, building a complete system based on uCOS-II from the ground up.

Anzma provide the trainees with a Kit based on ARM Cortex. Knowing that trainees already have good understanding of the boards peripherals, a break-through idea emerged to add 3 hours to the RTOS track and let the trainees experience programming uCOS-II on Anzma Kit.

In my visit, I suggested to port uCOS-II V2.86 to their Kit. After 5 hours and starting with a uCOS-II ported to the Cortex architecture, I managed to do board porting and coming up with an example that moved the trainees from the run for ever loop to multi-tasking programming.

The example consisted of many tasks; the first task was to do the system initialization. The second task simply blinked the LEDs on the board in a constant sequence. The timing was depending on uCOS-II time services rather than the simple delay routines. This made the timing independent on the beneath hardware. The third task was a periodic task that continually displays the ADC reading on the hyper terminal. The fourth task was to display the time on the screen and updates it every second. This task gets the data updated from the RTC ISR. The trick was to add the time setting feature using the two push buttons on the board. The first button was to select the field to update (hours, minutes, or seconds) and the second button was to increment the value. To accomplish this task, we created 2 tasks and added to 2 ISRs. The first task was responsible for blinking the selected field. The second was responsible for calculating the new time value before sending it to the Display task.

The example demonstrated many of uCOS-II services. Services included task management, mutex management, event flag management, and time management services. In addition, it demonstrated how to write ISRs under uCOS-II and how they can communicate with tasks.