VHDL 360, Simulation using ISIM

• Creating Project
• Interactive Simulation

Simulation Using Isim

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VHDL 360, FPGA Programming

• Creating Project
• Importing VHDL Files
• Assigning FPGA Pins
• Creating Programming File
• Configuring the Device
• Selecting the Programming File
• Programming the FPGA

Fpga programming

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VHDL 360, Post Place and Route Simulation

• Compile Simulation Libraries
• Post PAR Simulation

Post Place and Route Simulion

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VHDL 360, Structural Description

• How to Create Your Generic DU?
• Generic Clause
• Exercise 1: N Input OR Gate
• Exercise 2: N Input AND Gate
• Structural Description
• Structural Modeling
• Component Instantiation
• Exercise 3: Use T-FF to Create a 2-Bit Counter
• Testbench
• Stimulus Generation
• Monitors
• Generate Statement
• Exercise 4: Create N-Bit Shift Register
• VHDL Configurations

Building Hierarchy

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VHDL 360, Modeling Finite State Machines (FSMs)

• What is a FSM?
• State Machine
• Moore FSM
• Moore Implementation
• Mealy FSM
• Mealy Implementation
• FSM in VHDL
• Next State Logic
• Current State Logic
• Assigning Moore Outputs
• Assigning Mealy Outputs
• Moore vs. Mealy
• FSM Tips
• Example
• Exercise 1: Simple Control Unit
• State Machine Encoding
• Exercise 2: Traffic Light Controller

Modeling FSMs

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VHDL 360, Synthesis Examples

• Introduction
• Synthesize and Learn
• Combinational Logic
• Latch Inference
• Sequential Logic
• Flip-flop Interference

Synthesis Examples

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VHDL 360, Data Types and Operators Continued

• Operators
• Operators Precedence
• Logical Operators
• Addition Operators
• Relational Operators
• Shift Operators
• Multiplication Operators
• Miscellaneous Operators
• Aggregate
• Attributes

Data types and Operators Continued

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VHDL 360, Synthesis Using ISE

• New Project
• Project Setting
• Import Files to ISE
• Synthesize Design Unit
• View RTL
• Synthesis Report

Synthesis Using ISE

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VHDL 360, Data Types and Operators

• Data Types
• Scalar Types
• Composite Types
• Exercise 1: Modeling a 16x16 ROM Memory
• Exercise 2: Modeling 1024x8 RAM Memory

Data types and Operators

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VHDL 360, Write More Complex Models Continued

• While Loop
• For Loop
• Exercise 1: Serial In Parallel Out
• Wait Statement
• Conversion Functions
• Lab 1.a: Write the Code for a Fibonacci Sequence
• Lab 1.b: Write the Code for Knight Rider LEDs

Writing more complex models (continued)

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VHDL 360, Simulation Using ModelSim

• Command Line Simulation
  
• Compile and Simulate
  
• Add Signals to Wave
• Applying Inputs
• Run Simulation
• Make Files
• Interactive Simulation

Simulation using model sim

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VHDL 360, Write More Complex Models

• Statements
• Process Description
  
• Sequential Assignments
  
• Data Objects
  
• Objects Scope
  
• Data Objects Example
  
• Skills Check
• Case Statement
• Exercise 1: 2x4 by Decoder
• If Statement
• Exercise 2: D FF with Synchronous Reset
• Exercise 3: Simple Comparator

Writing more complex models

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VHDL 360, Create Your First Model for a Simple Logic Circuit

• Entity
• Exercise 1: Write the Entity of a 1-bit Full Adder
  
• Architecture
• Internal Signals
• Expressions & Operators
• Exercise 2: Write the Architecture of a 1-bit Full Adder
  
• With-Select
• When-Else
• Exercise 3: Write the Entity and Architecture of 2x4 Decoder and 4x2 Encoder using With-Select and When-Else

Create your first model for a simple logic circuit

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VHDL 360, Introduction to VHDL

• What is VHDL?
• VHDL History
• Uses of VHDL
• Basic Design Flow
• VHDL Model
• Entity
• Architecture
  
• Concurrency
• Simple Example

Introduction to VHDL

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VHDL 360, a Contribution from the SAMs

About VHDL

VHDL is a powerful language developed in the 1980's by the US department of defense, afterwards adopted by the IEEE to be a standard in 1987. Many enhancements & new features were added afterwards in the 1993, 2002 & 2008 standards...

VHDL is widely used around the word in the design & verification processes of High & Very High Scale integrated circuits design (HSI & VHSI)

About the Free Course, VHDL 360

VHDL 360 is a free course. During the course, SAMS will try to guide & teach students how to write efficient VHDL code to model digital circuits, the course outline will be as follows:

• Introduction to VHDL
• Writing 1st Model
• Writing more complex Models
• Building Hierarchy
• Modeling FSMs & Memories
• Code Reuse
• Verification

The course is based on VHDL IEEE 1076 - 1993 standard. It is vendor independent. Any text editor and tools you have license for can be used. Any consultation with regards to tools setup or support will not be provided and trainees should consult their own vendor for any of the issues or problems they face with this regards.

Feel free to post any comments, questions, and feedback through the blog. We promise to answer your questions as soon as possible Insha'Allah.

This VHDL course is for free use as long as the original copyright is reproduced. Feel free to spread and share. Knowledge is every body's right just like air and water.